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Macros
#define	STM32F4xx_MCUCONF
#define	STM32F427_MCUCONF
#define	STM32F429_MCUCONF
#define	STM32F437_MCUCONF
#define	STM32F439_MCUCONF
#define	STM32_NO_INIT   FALSE
#define	STM32_PVD_ENABLE   FALSE
#define	STM32_PLS   STM32_PLS_LEV0
#define	STM32_BKPRAM_ENABLE   FALSE
#define	STM32_HSI_ENABLED   TRUE
#define	STM32_LSI_ENABLED   TRUE
#define	STM32_HSE_ENABLED   TRUE
#define	STM32_LSE_ENABLED   FALSE
#define	STM32_CLOCK48_REQUIRED   TRUE
#define	STM32_SW   STM32_SW_PLL
#define	STM32_PLLSRC   STM32_PLLSRC_HSE
#define	STM32_PLLM_VALUE   8
#define	STM32_PLLN_VALUE   336
#define	STM32_PLLP_VALUE   2
#define	STM32_PLLQ_VALUE   7
#define	STM32_HPRE   STM32_HPRE_DIV1
#define	STM32_PPRE1   STM32_PPRE1_DIV4
#define	STM32_PPRE2   STM32_PPRE2_DIV2
#define	STM32_RTCSEL   STM32_RTCSEL_LSI
#define	STM32_RTCPRE_VALUE   8
#define	STM32_MCO1SEL   STM32_MCO1SEL_HSI
#define	STM32_MCO1PRE   STM32_MCO1PRE_DIV1
#define	STM32_MCO2SEL   STM32_MCO2SEL_SYSCLK
#define	STM32_MCO2PRE   STM32_MCO2PRE_DIV5
#define	STM32_I2SSRC   STM32_I2SSRC_CKIN
#define	STM32_PLLI2SN_VALUE   192
#define	STM32_PLLI2SR_VALUE   5
#define	STM32_IRQ_EXTI0_PRIORITY   6
#define	STM32_IRQ_EXTI1_PRIORITY   6
#define	STM32_IRQ_EXTI2_PRIORITY   6
#define	STM32_IRQ_EXTI3_PRIORITY   6
#define	STM32_IRQ_EXTI4_PRIORITY   6
#define	STM32_IRQ_EXTI5_9_PRIORITY   6
#define	STM32_IRQ_EXTI10_15_PRIORITY   6
#define	STM32_IRQ_EXTI16_PRIORITY   6
#define	STM32_IRQ_EXTI17_PRIORITY   15
#define	STM32_IRQ_EXTI18_PRIORITY   6
#define	STM32_IRQ_EXTI19_PRIORITY   6
#define	STM32_IRQ_EXTI20_PRIORITY   6
#define	STM32_IRQ_EXTI21_PRIORITY   15
#define	STM32_IRQ_EXTI22_PRIORITY   15
#define	STM32_IRQ_TIM1_BRK_TIM9_PRIORITY   7
#define	STM32_IRQ_TIM1_UP_TIM10_PRIORITY   7
#define	STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY   7
#define	STM32_IRQ_TIM1_CC_PRIORITY   7
#define	STM32_IRQ_TIM2_PRIORITY   7
#define	STM32_IRQ_TIM3_PRIORITY   7
#define	STM32_IRQ_TIM4_PRIORITY   7
#define	STM32_IRQ_TIM5_PRIORITY   7
#define	STM32_IRQ_TIM6_PRIORITY   7
#define	STM32_IRQ_TIM7_PRIORITY   7
#define	STM32_IRQ_TIM8_BRK_TIM12_PRIORITY   7
#define	STM32_IRQ_TIM8_UP_TIM13_PRIORITY   7
#define	STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY   7
#define	STM32_IRQ_TIM8_CC_PRIORITY   7
#define	STM32_IRQ_USART1_PRIORITY   12
#define	STM32_IRQ_USART2_PRIORITY   12
#define	STM32_IRQ_USART3_PRIORITY   12
#define	STM32_IRQ_UART4_PRIORITY   12
#define	STM32_IRQ_UART5_PRIORITY   12
#define	STM32_IRQ_USART6_PRIORITY   12
#define	STM32_IRQ_UART7_PRIORITY   12
#define	STM32_IRQ_UART8_PRIORITY   12
#define	STM32_ADC_ADCPRE   ADC_CCR_ADCPRE_DIV4
#define	STM32_ADC_USE_ADC1   TRUE
#define	STM32_ADC_USE_ADC2   FALSE
#define	STM32_ADC_USE_ADC3   FALSE
#define	STM32_ADC_ADC1_DMA_STREAM   STM32_DMA_STREAM_ID(2, 4)
#define	STM32_ADC_ADC2_DMA_STREAM   STM32_DMA_STREAM_ID(2, 2)
#define	STM32_ADC_ADC3_DMA_STREAM   STM32_DMA_STREAM_ID(2, 1)
#define	STM32_ADC_ADC1_DMA_PRIORITY   2
#define	STM32_ADC_ADC2_DMA_PRIORITY   2
#define	STM32_ADC_ADC3_DMA_PRIORITY   2
#define	STM32_ADC_IRQ_PRIORITY   6
#define	STM32_ADC_ADC1_DMA_IRQ_PRIORITY   6
#define	STM32_ADC_ADC2_DMA_IRQ_PRIORITY   6
#define	STM32_ADC_ADC3_DMA_IRQ_PRIORITY   6
#define	STM32_CAN_USE_CAN1   FALSE
#define	STM32_CAN_USE_CAN2   FALSE
#define	STM32_CAN_CAN1_IRQ_PRIORITY   11
#define	STM32_CAN_CAN2_IRQ_PRIORITY   11
#define	STM32_DAC_DUAL_MODE   FALSE
#define	STM32_DAC_USE_DAC1_CH1   FALSE
#define	STM32_DAC_USE_DAC1_CH2   FALSE
#define	STM32_DAC_DAC1_CH1_IRQ_PRIORITY   10
#define	STM32_DAC_DAC1_CH2_IRQ_PRIORITY   10
#define	STM32_DAC_DAC1_CH1_DMA_PRIORITY   2
#define	STM32_DAC_DAC1_CH2_DMA_PRIORITY   2
#define	STM32_DAC_DAC1_CH1_DMA_STREAM   STM32_DMA_STREAM_ID(1, 5)
#define	STM32_DAC_DAC1_CH2_DMA_STREAM   STM32_DMA_STREAM_ID(1, 6)
#define	STM32_GPT_USE_TIM1   FALSE
#define	STM32_GPT_USE_TIM2   FALSE
#define	STM32_GPT_USE_TIM3   TRUE
#define	STM32_GPT_USE_TIM4   TRUE
#define	STM32_GPT_USE_TIM5   FALSE
#define	STM32_GPT_USE_TIM6   FALSE
#define	STM32_GPT_USE_TIM7   FALSE
#define	STM32_GPT_USE_TIM8   FALSE
#define	STM32_GPT_USE_TIM9   FALSE
#define	STM32_GPT_USE_TIM10   FALSE
#define	STM32_GPT_USE_TIM11   FALSE
#define	STM32_GPT_USE_TIM12   FALSE
#define	STM32_GPT_USE_TIM13   FALSE
#define	STM32_GPT_USE_TIM14   FALSE
#define	STM32_I2C_USE_I2C1   FALSE
#define	STM32_I2C_USE_I2C2   FALSE
#define	STM32_I2C_USE_I2C3   FALSE
#define	STM32_I2C_BUSY_TIMEOUT   50
#define	STM32_I2C_I2C1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)
#define	STM32_I2C_I2C1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 6)
#define	STM32_I2C_I2C2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 2)
#define	STM32_I2C_I2C2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)
#define	STM32_I2C_I2C3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 2)
#define	STM32_I2C_I2C3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)
#define	STM32_I2C_I2C1_IRQ_PRIORITY   5
#define	STM32_I2C_I2C2_IRQ_PRIORITY   5
#define	STM32_I2C_I2C3_IRQ_PRIORITY   5
#define	STM32_I2C_I2C1_DMA_PRIORITY   3
#define	STM32_I2C_I2C2_DMA_PRIORITY   3
#define	STM32_I2C_I2C3_DMA_PRIORITY   3
#define	STM32_I2C_DMA_ERROR_HOOK(i2cp)   osalSysHalt("DMA failure")
#define	STM32_I2S_USE_SPI2   FALSE
#define	STM32_I2S_USE_SPI3   FALSE
#define	STM32_I2S_SPI2_IRQ_PRIORITY   10
#define	STM32_I2S_SPI3_IRQ_PRIORITY   10
#define	STM32_I2S_SPI2_DMA_PRIORITY   1
#define	STM32_I2S_SPI3_DMA_PRIORITY   1
#define	STM32_I2S_SPI2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 3)
#define	STM32_I2S_SPI2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)
#define	STM32_I2S_SPI3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)
#define	STM32_I2S_SPI3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)
#define	STM32_I2S_DMA_ERROR_HOOK(i2sp)   osalSysHalt("DMA failure")
#define	STM32_ICU_USE_TIM1   FALSE
#define	STM32_ICU_USE_TIM2   FALSE
#define	STM32_ICU_USE_TIM3   FALSE
#define	STM32_ICU_USE_TIM4   FALSE
#define	STM32_ICU_USE_TIM5   FALSE
#define	STM32_ICU_USE_TIM8   FALSE
#define	STM32_ICU_USE_TIM9   FALSE
#define	STM32_ICU_USE_TIM10   FALSE
#define	STM32_ICU_USE_TIM11   FALSE
#define	STM32_ICU_USE_TIM12   FALSE
#define	STM32_ICU_USE_TIM13   FALSE
#define	STM32_ICU_USE_TIM14   FALSE
#define	STM32_MAC_TRANSMIT_BUFFERS   2
#define	STM32_MAC_RECEIVE_BUFFERS   4
#define	STM32_MAC_BUFFERS_SIZE   1522
#define	STM32_MAC_PHY_TIMEOUT   100
#define	STM32_MAC_ETH1_CHANGE_PHY_STATE   TRUE
#define	STM32_MAC_ETH1_IRQ_PRIORITY   13
#define	STM32_MAC_IP_CHECKSUM_OFFLOAD   0
#define	STM32_PWM_USE_TIM1   FALSE
#define	STM32_PWM_USE_TIM2   FALSE
#define	STM32_PWM_USE_TIM3   FALSE
#define	STM32_PWM_USE_TIM4   FALSE
#define	STM32_PWM_USE_TIM5   FALSE
#define	STM32_PWM_USE_TIM8   FALSE
#define	STM32_PWM_USE_TIM9   FALSE
#define	STM32_PWM_USE_TIM10   FALSE
#define	STM32_PWM_USE_TIM11   FALSE
#define	STM32_PWM_USE_TIM12   FALSE
#define	STM32_PWM_USE_TIM13   FALSE
#define	STM32_PWM_USE_TIM14   FALSE
#define	STM32_RTC_PRESA_VALUE   32
#define	STM32_RTC_PRESS_VALUE   1024
#define	STM32_RTC_CR_INIT   0
#define	STM32_RTC_TAMPCR_INIT   0
#define	STM32_SDC_SDIO_DMA_PRIORITY   3
#define	STM32_SDC_SDIO_IRQ_PRIORITY   9
#define	STM32_SDC_WRITE_TIMEOUT_MS   1000
#define	STM32_SDC_READ_TIMEOUT_MS   1000
#define	STM32_SDC_CLOCK_ACTIVATION_DELAY   10
#define	STM32_SDC_SDIO_UNALIGNED_SUPPORT   TRUE
#define	STM32_SDC_SDIO_DMA_STREAM   STM32_DMA_STREAM_ID(2, 3)
#define	STM32_SERIAL_USE_USART1   TRUE
#define	STM32_SERIAL_USE_USART2   TRUE
#define	STM32_SERIAL_USE_USART3   TRUE
#define	STM32_SERIAL_USE_UART4   TRUE
#define	STM32_SERIAL_USE_UART5   FALSE
#define	STM32_SERIAL_USE_USART6   FALSE
#define	STM32_SPI_USE_SPI1   TRUE
#define	STM32_SPI_USE_SPI2   FALSE
#define	STM32_SPI_USE_SPI3   TRUE
#define	STM32_SPI_USE_SPI4   FALSE
#define	STM32_SPI_USE_SPI5   FALSE
#define	STM32_SPI_USE_SPI6   FALSE
#define	STM32_SPI_SPI1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 0)
#define	STM32_SPI_SPI1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 3)
#define	STM32_SPI_SPI2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 3)
#define	STM32_SPI_SPI2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)
#define	STM32_SPI_SPI3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)
#define	STM32_SPI_SPI3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)
#define	STM32_SPI_SPI4_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 0)
#define	STM32_SPI_SPI4_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 1)
#define	STM32_SPI_SPI5_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 3)
#define	STM32_SPI_SPI5_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 4)
#define	STM32_SPI_SPI6_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 6)
#define	STM32_SPI_SPI6_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 5)
#define	STM32_SPI_SPI1_DMA_PRIORITY   1
#define	STM32_SPI_SPI2_DMA_PRIORITY   1
#define	STM32_SPI_SPI3_DMA_PRIORITY   1
#define	STM32_SPI_SPI4_DMA_PRIORITY   1
#define	STM32_SPI_SPI5_DMA_PRIORITY   1
#define	STM32_SPI_SPI6_DMA_PRIORITY   1
#define	STM32_SPI_SPI1_IRQ_PRIORITY   10
#define	STM32_SPI_SPI2_IRQ_PRIORITY   10
#define	STM32_SPI_SPI3_IRQ_PRIORITY   10
#define	STM32_SPI_SPI4_IRQ_PRIORITY   10
#define	STM32_SPI_SPI5_IRQ_PRIORITY   10
#define	STM32_SPI_SPI6_IRQ_PRIORITY   10
#define	STM32_SPI_DMA_ERROR_HOOK(spip)   osalSysHalt("DMA failure")
#define	STM32_ST_IRQ_PRIORITY   8
#define	STM32_ST_USE_TIMER   5
#define	STM32_UART_USE_USART1   FALSE
#define	STM32_UART_USE_USART2   FALSE
#define	STM32_UART_USE_USART3   FALSE
#define	STM32_UART_USE_UART4   FALSE
#define	STM32_UART_USE_UART5   FALSE
#define	STM32_UART_USE_USART6   FALSE
#define	STM32_UART_USART1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 5)
#define	STM32_UART_USART1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 7)
#define	STM32_UART_USART2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 5)
#define	STM32_UART_USART2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 6)
#define	STM32_UART_USART3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 1)
#define	STM32_UART_USART3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 3)
#define	STM32_UART_UART4_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 2)
#define	STM32_UART_UART4_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)
#define	STM32_UART_UART5_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)
#define	STM32_UART_UART5_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)
#define	STM32_UART_USART6_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 2)
#define	STM32_UART_USART6_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 7)
#define	STM32_UART_USART1_DMA_PRIORITY   0
#define	STM32_UART_USART2_DMA_PRIORITY   0
#define	STM32_UART_USART3_DMA_PRIORITY   0
#define	STM32_UART_UART4_DMA_PRIORITY   0
#define	STM32_UART_UART5_DMA_PRIORITY   0
#define	STM32_UART_USART6_DMA_PRIORITY   0
#define	STM32_UART_DMA_ERROR_HOOK(uartp)   osalSysHalt("DMA failure")
#define	STM32_USB_USE_OTG1   TRUE
#define	STM32_USB_USE_OTG2   FALSE
#define	STM32_USB_OTG1_IRQ_PRIORITY   11
#define	STM32_USB_OTG2_IRQ_PRIORITY   14
#define	STM32_USB_OTG1_RX_FIFO_SIZE   512
#define	STM32_USB_OTG2_RX_FIFO_SIZE   1024
#define	STM32_USB_HOST_WAKEUP_DURATION   2
#define	STM32_OTG1_VBUS_SENSING   FALSE
#define	STM32_WDG_USE_IWDG   FALSE

Documentation des macros

STM32_ADC_ADC1_DMA_IRQ_PRIORITY

#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY   6

STM32_ADC_ADC1_DMA_PRIORITY

#define STM32_ADC_ADC1_DMA_PRIORITY   2

STM32_ADC_ADC1_DMA_STREAM

#define STM32_ADC_ADC1_DMA_STREAM   STM32_DMA_STREAM_ID(2, 4)

STM32_ADC_ADC2_DMA_IRQ_PRIORITY

#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY   6

STM32_ADC_ADC2_DMA_PRIORITY

#define STM32_ADC_ADC2_DMA_PRIORITY   2

STM32_ADC_ADC2_DMA_STREAM

#define STM32_ADC_ADC2_DMA_STREAM   STM32_DMA_STREAM_ID(2, 2)

STM32_ADC_ADC3_DMA_IRQ_PRIORITY

#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY   6

STM32_ADC_ADC3_DMA_PRIORITY

#define STM32_ADC_ADC3_DMA_PRIORITY   2

STM32_ADC_ADC3_DMA_STREAM

#define STM32_ADC_ADC3_DMA_STREAM   STM32_DMA_STREAM_ID(2, 1)

STM32_ADC_ADCPRE

#define STM32_ADC_ADCPRE   ADC_CCR_ADCPRE_DIV4

STM32_ADC_IRQ_PRIORITY

#define STM32_ADC_IRQ_PRIORITY   6

STM32_ADC_USE_ADC1

#define STM32_ADC_USE_ADC1   TRUE

STM32_ADC_USE_ADC2

#define STM32_ADC_USE_ADC2   FALSE

STM32_ADC_USE_ADC3

#define STM32_ADC_USE_ADC3   FALSE

STM32_BKPRAM_ENABLE

#define STM32_BKPRAM_ENABLE   FALSE

STM32_CAN_CAN1_IRQ_PRIORITY

#define STM32_CAN_CAN1_IRQ_PRIORITY   11

STM32_CAN_CAN2_IRQ_PRIORITY

#define STM32_CAN_CAN2_IRQ_PRIORITY   11

STM32_CAN_USE_CAN1

#define STM32_CAN_USE_CAN1   FALSE

STM32_CAN_USE_CAN2

#define STM32_CAN_USE_CAN2   FALSE

STM32_CLOCK48_REQUIRED

#define STM32_CLOCK48_REQUIRED   TRUE

STM32_DAC_DAC1_CH1_DMA_PRIORITY

#define STM32_DAC_DAC1_CH1_DMA_PRIORITY   2

STM32_DAC_DAC1_CH1_DMA_STREAM

#define STM32_DAC_DAC1_CH1_DMA_STREAM   STM32_DMA_STREAM_ID(1, 5)

STM32_DAC_DAC1_CH1_IRQ_PRIORITY

#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY   10

STM32_DAC_DAC1_CH2_DMA_PRIORITY

#define STM32_DAC_DAC1_CH2_DMA_PRIORITY   2

STM32_DAC_DAC1_CH2_DMA_STREAM

#define STM32_DAC_DAC1_CH2_DMA_STREAM   STM32_DMA_STREAM_ID(1, 6)

STM32_DAC_DAC1_CH2_IRQ_PRIORITY

#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY   10

STM32_DAC_DUAL_MODE

#define STM32_DAC_DUAL_MODE   FALSE

STM32_DAC_USE_DAC1_CH1

#define STM32_DAC_USE_DAC1_CH1   FALSE

STM32_DAC_USE_DAC1_CH2

#define STM32_DAC_USE_DAC1_CH2   FALSE

STM32_GPT_USE_TIM1

#define STM32_GPT_USE_TIM1   FALSE

STM32_GPT_USE_TIM10

#define STM32_GPT_USE_TIM10   FALSE

STM32_GPT_USE_TIM11

#define STM32_GPT_USE_TIM11   FALSE

STM32_GPT_USE_TIM12

#define STM32_GPT_USE_TIM12   FALSE

STM32_GPT_USE_TIM13

#define STM32_GPT_USE_TIM13   FALSE

STM32_GPT_USE_TIM14

#define STM32_GPT_USE_TIM14   FALSE

STM32_GPT_USE_TIM2

#define STM32_GPT_USE_TIM2   FALSE

STM32_GPT_USE_TIM3

#define STM32_GPT_USE_TIM3   TRUE

STM32_GPT_USE_TIM4

#define STM32_GPT_USE_TIM4   TRUE

STM32_GPT_USE_TIM5

#define STM32_GPT_USE_TIM5   FALSE

STM32_GPT_USE_TIM6

#define STM32_GPT_USE_TIM6   FALSE

STM32_GPT_USE_TIM7

#define STM32_GPT_USE_TIM7   FALSE

STM32_GPT_USE_TIM8

#define STM32_GPT_USE_TIM8   FALSE

STM32_GPT_USE_TIM9

#define STM32_GPT_USE_TIM9   FALSE

STM32_HPRE

#define STM32_HPRE   STM32_HPRE_DIV1

STM32_HSE_ENABLED

#define STM32_HSE_ENABLED   TRUE

STM32_HSI_ENABLED

#define STM32_HSI_ENABLED   TRUE

STM32_I2C_BUSY_TIMEOUT

#define STM32_I2C_BUSY_TIMEOUT   50

STM32_I2C_DMA_ERROR_HOOK

#define STM32_I2C_DMA_ERROR_HOOK

(

i2cp

)

osalSysHalt("DMA failure")

STM32_I2C_I2C1_DMA_PRIORITY

#define STM32_I2C_I2C1_DMA_PRIORITY   3

STM32_I2C_I2C1_IRQ_PRIORITY

#define STM32_I2C_I2C1_IRQ_PRIORITY   5

STM32_I2C_I2C1_RX_DMA_STREAM

#define STM32_I2C_I2C1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)

STM32_I2C_I2C1_TX_DMA_STREAM

#define STM32_I2C_I2C1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 6)

STM32_I2C_I2C2_DMA_PRIORITY

#define STM32_I2C_I2C2_DMA_PRIORITY   3

STM32_I2C_I2C2_IRQ_PRIORITY

#define STM32_I2C_I2C2_IRQ_PRIORITY   5

STM32_I2C_I2C2_RX_DMA_STREAM

#define STM32_I2C_I2C2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 2)

STM32_I2C_I2C2_TX_DMA_STREAM

#define STM32_I2C_I2C2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)

STM32_I2C_I2C3_DMA_PRIORITY

#define STM32_I2C_I2C3_DMA_PRIORITY   3

STM32_I2C_I2C3_IRQ_PRIORITY

#define STM32_I2C_I2C3_IRQ_PRIORITY   5

STM32_I2C_I2C3_RX_DMA_STREAM

#define STM32_I2C_I2C3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 2)

STM32_I2C_I2C3_TX_DMA_STREAM

#define STM32_I2C_I2C3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)

STM32_I2C_USE_I2C1

#define STM32_I2C_USE_I2C1   FALSE

STM32_I2C_USE_I2C2

#define STM32_I2C_USE_I2C2   FALSE

STM32_I2C_USE_I2C3

#define STM32_I2C_USE_I2C3   FALSE

STM32_I2S_DMA_ERROR_HOOK

#define STM32_I2S_DMA_ERROR_HOOK

(

i2sp

)

osalSysHalt("DMA failure")

STM32_I2S_SPI2_DMA_PRIORITY

#define STM32_I2S_SPI2_DMA_PRIORITY   1

STM32_I2S_SPI2_IRQ_PRIORITY

#define STM32_I2S_SPI2_IRQ_PRIORITY   10

STM32_I2S_SPI2_RX_DMA_STREAM

#define STM32_I2S_SPI2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 3)

STM32_I2S_SPI2_TX_DMA_STREAM

#define STM32_I2S_SPI2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)

STM32_I2S_SPI3_DMA_PRIORITY

#define STM32_I2S_SPI3_DMA_PRIORITY   1

STM32_I2S_SPI3_IRQ_PRIORITY

#define STM32_I2S_SPI3_IRQ_PRIORITY   10

STM32_I2S_SPI3_RX_DMA_STREAM

#define STM32_I2S_SPI3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)

STM32_I2S_SPI3_TX_DMA_STREAM

#define STM32_I2S_SPI3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)

STM32_I2S_USE_SPI2

#define STM32_I2S_USE_SPI2   FALSE

STM32_I2S_USE_SPI3

#define STM32_I2S_USE_SPI3   FALSE

STM32_I2SSRC

#define STM32_I2SSRC   STM32_I2SSRC_CKIN

STM32_ICU_USE_TIM1

#define STM32_ICU_USE_TIM1   FALSE

STM32_ICU_USE_TIM10

#define STM32_ICU_USE_TIM10   FALSE

STM32_ICU_USE_TIM11

#define STM32_ICU_USE_TIM11   FALSE

STM32_ICU_USE_TIM12

#define STM32_ICU_USE_TIM12   FALSE

STM32_ICU_USE_TIM13

#define STM32_ICU_USE_TIM13   FALSE

STM32_ICU_USE_TIM14

#define STM32_ICU_USE_TIM14   FALSE

STM32_ICU_USE_TIM2

#define STM32_ICU_USE_TIM2   FALSE

STM32_ICU_USE_TIM3

#define STM32_ICU_USE_TIM3   FALSE

STM32_ICU_USE_TIM4

#define STM32_ICU_USE_TIM4   FALSE

STM32_ICU_USE_TIM5

#define STM32_ICU_USE_TIM5   FALSE

STM32_ICU_USE_TIM8

#define STM32_ICU_USE_TIM8   FALSE

STM32_ICU_USE_TIM9

#define STM32_ICU_USE_TIM9   FALSE

STM32_IRQ_EXTI0_PRIORITY

#define STM32_IRQ_EXTI0_PRIORITY   6

STM32_IRQ_EXTI10_15_PRIORITY

#define STM32_IRQ_EXTI10_15_PRIORITY   6

STM32_IRQ_EXTI16_PRIORITY

#define STM32_IRQ_EXTI16_PRIORITY   6

STM32_IRQ_EXTI17_PRIORITY

#define STM32_IRQ_EXTI17_PRIORITY   15

STM32_IRQ_EXTI18_PRIORITY

#define STM32_IRQ_EXTI18_PRIORITY   6

STM32_IRQ_EXTI19_PRIORITY

#define STM32_IRQ_EXTI19_PRIORITY   6

STM32_IRQ_EXTI1_PRIORITY

#define STM32_IRQ_EXTI1_PRIORITY   6

STM32_IRQ_EXTI20_PRIORITY

#define STM32_IRQ_EXTI20_PRIORITY   6

STM32_IRQ_EXTI21_PRIORITY

#define STM32_IRQ_EXTI21_PRIORITY   15

STM32_IRQ_EXTI22_PRIORITY

#define STM32_IRQ_EXTI22_PRIORITY   15

STM32_IRQ_EXTI2_PRIORITY

#define STM32_IRQ_EXTI2_PRIORITY   6

STM32_IRQ_EXTI3_PRIORITY

#define STM32_IRQ_EXTI3_PRIORITY   6

STM32_IRQ_EXTI4_PRIORITY

#define STM32_IRQ_EXTI4_PRIORITY   6

STM32_IRQ_EXTI5_9_PRIORITY

#define STM32_IRQ_EXTI5_9_PRIORITY   6

STM32_IRQ_TIM1_BRK_TIM9_PRIORITY

#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY   7

STM32_IRQ_TIM1_CC_PRIORITY

#define STM32_IRQ_TIM1_CC_PRIORITY   7

STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY

#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY   7

STM32_IRQ_TIM1_UP_TIM10_PRIORITY

#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY   7

STM32_IRQ_TIM2_PRIORITY

#define STM32_IRQ_TIM2_PRIORITY   7

STM32_IRQ_TIM3_PRIORITY

#define STM32_IRQ_TIM3_PRIORITY   7

STM32_IRQ_TIM4_PRIORITY

#define STM32_IRQ_TIM4_PRIORITY   7

STM32_IRQ_TIM5_PRIORITY

#define STM32_IRQ_TIM5_PRIORITY   7

STM32_IRQ_TIM6_PRIORITY

#define STM32_IRQ_TIM6_PRIORITY   7

STM32_IRQ_TIM7_PRIORITY

#define STM32_IRQ_TIM7_PRIORITY   7

STM32_IRQ_TIM8_BRK_TIM12_PRIORITY

#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY   7

STM32_IRQ_TIM8_CC_PRIORITY

#define STM32_IRQ_TIM8_CC_PRIORITY   7

STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY

#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY   7

STM32_IRQ_TIM8_UP_TIM13_PRIORITY

#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY   7

STM32_IRQ_UART4_PRIORITY

#define STM32_IRQ_UART4_PRIORITY   12

STM32_IRQ_UART5_PRIORITY

#define STM32_IRQ_UART5_PRIORITY   12

STM32_IRQ_UART7_PRIORITY

#define STM32_IRQ_UART7_PRIORITY   12

STM32_IRQ_UART8_PRIORITY

#define STM32_IRQ_UART8_PRIORITY   12

STM32_IRQ_USART1_PRIORITY

#define STM32_IRQ_USART1_PRIORITY   12

STM32_IRQ_USART2_PRIORITY

#define STM32_IRQ_USART2_PRIORITY   12

STM32_IRQ_USART3_PRIORITY

#define STM32_IRQ_USART3_PRIORITY   12

STM32_IRQ_USART6_PRIORITY

#define STM32_IRQ_USART6_PRIORITY   12

STM32_LSE_ENABLED

#define STM32_LSE_ENABLED   FALSE

STM32_LSI_ENABLED

#define STM32_LSI_ENABLED   TRUE

STM32_MAC_BUFFERS_SIZE

#define STM32_MAC_BUFFERS_SIZE   1522

STM32_MAC_ETH1_CHANGE_PHY_STATE

#define STM32_MAC_ETH1_CHANGE_PHY_STATE   TRUE

STM32_MAC_ETH1_IRQ_PRIORITY

#define STM32_MAC_ETH1_IRQ_PRIORITY   13

STM32_MAC_IP_CHECKSUM_OFFLOAD

#define STM32_MAC_IP_CHECKSUM_OFFLOAD   0

STM32_MAC_PHY_TIMEOUT

#define STM32_MAC_PHY_TIMEOUT   100

STM32_MAC_RECEIVE_BUFFERS

#define STM32_MAC_RECEIVE_BUFFERS   4

STM32_MAC_TRANSMIT_BUFFERS

#define STM32_MAC_TRANSMIT_BUFFERS   2

STM32_MCO1PRE

#define STM32_MCO1PRE   STM32_MCO1PRE_DIV1

STM32_MCO1SEL

#define STM32_MCO1SEL   STM32_MCO1SEL_HSI

STM32_MCO2PRE

#define STM32_MCO2PRE   STM32_MCO2PRE_DIV5

STM32_MCO2SEL

#define STM32_MCO2SEL   STM32_MCO2SEL_SYSCLK

STM32_NO_INIT

#define STM32_NO_INIT   FALSE

STM32_OTG1_VBUS_SENSING

#define STM32_OTG1_VBUS_SENSING   FALSE

STM32_PLLI2SN_VALUE

#define STM32_PLLI2SN_VALUE   192

STM32_PLLI2SR_VALUE

#define STM32_PLLI2SR_VALUE   5

STM32_PLLM_VALUE

#define STM32_PLLM_VALUE   8

STM32_PLLN_VALUE

#define STM32_PLLN_VALUE   336

STM32_PLLP_VALUE

#define STM32_PLLP_VALUE   2

STM32_PLLQ_VALUE

#define STM32_PLLQ_VALUE   7

STM32_PLLSRC

#define STM32_PLLSRC   STM32_PLLSRC_HSE

STM32_PLS

#define STM32_PLS   STM32_PLS_LEV0

STM32_PPRE1

#define STM32_PPRE1   STM32_PPRE1_DIV4

STM32_PPRE2

#define STM32_PPRE2   STM32_PPRE2_DIV2

STM32_PVD_ENABLE

#define STM32_PVD_ENABLE   FALSE

STM32_PWM_USE_TIM1

#define STM32_PWM_USE_TIM1   FALSE

STM32_PWM_USE_TIM10

#define STM32_PWM_USE_TIM10   FALSE

STM32_PWM_USE_TIM11

#define STM32_PWM_USE_TIM11   FALSE

STM32_PWM_USE_TIM12

#define STM32_PWM_USE_TIM12   FALSE

STM32_PWM_USE_TIM13

#define STM32_PWM_USE_TIM13   FALSE

STM32_PWM_USE_TIM14

#define STM32_PWM_USE_TIM14   FALSE

STM32_PWM_USE_TIM2

#define STM32_PWM_USE_TIM2   FALSE

STM32_PWM_USE_TIM3

#define STM32_PWM_USE_TIM3   FALSE

STM32_PWM_USE_TIM4

#define STM32_PWM_USE_TIM4   FALSE

STM32_PWM_USE_TIM5

#define STM32_PWM_USE_TIM5   FALSE

STM32_PWM_USE_TIM8

#define STM32_PWM_USE_TIM8   FALSE

STM32_PWM_USE_TIM9

#define STM32_PWM_USE_TIM9   FALSE

STM32_RTC_CR_INIT

#define STM32_RTC_CR_INIT   0

STM32_RTC_PRESA_VALUE

#define STM32_RTC_PRESA_VALUE   32

STM32_RTC_PRESS_VALUE

#define STM32_RTC_PRESS_VALUE   1024

STM32_RTC_TAMPCR_INIT

#define STM32_RTC_TAMPCR_INIT   0

STM32_RTCPRE_VALUE

#define STM32_RTCPRE_VALUE   8

STM32_RTCSEL

#define STM32_RTCSEL   STM32_RTCSEL_LSI

STM32_SDC_CLOCK_ACTIVATION_DELAY

#define STM32_SDC_CLOCK_ACTIVATION_DELAY   10

STM32_SDC_READ_TIMEOUT_MS

#define STM32_SDC_READ_TIMEOUT_MS   1000

STM32_SDC_SDIO_DMA_PRIORITY

#define STM32_SDC_SDIO_DMA_PRIORITY   3

STM32_SDC_SDIO_DMA_STREAM

#define STM32_SDC_SDIO_DMA_STREAM   STM32_DMA_STREAM_ID(2, 3)

STM32_SDC_SDIO_IRQ_PRIORITY

#define STM32_SDC_SDIO_IRQ_PRIORITY   9

STM32_SDC_SDIO_UNALIGNED_SUPPORT

#define STM32_SDC_SDIO_UNALIGNED_SUPPORT   TRUE

STM32_SDC_WRITE_TIMEOUT_MS

#define STM32_SDC_WRITE_TIMEOUT_MS   1000

STM32_SERIAL_USE_UART4

#define STM32_SERIAL_USE_UART4   TRUE

STM32_SERIAL_USE_UART5

#define STM32_SERIAL_USE_UART5   FALSE

STM32_SERIAL_USE_USART1

#define STM32_SERIAL_USE_USART1   TRUE

STM32_SERIAL_USE_USART2

#define STM32_SERIAL_USE_USART2   TRUE

STM32_SERIAL_USE_USART3

#define STM32_SERIAL_USE_USART3   TRUE

STM32_SERIAL_USE_USART6

#define STM32_SERIAL_USE_USART6   FALSE

STM32_SPI_DMA_ERROR_HOOK

#define STM32_SPI_DMA_ERROR_HOOK

(

spip

)

osalSysHalt("DMA failure")

STM32_SPI_SPI1_DMA_PRIORITY

#define STM32_SPI_SPI1_DMA_PRIORITY   1

STM32_SPI_SPI1_IRQ_PRIORITY

#define STM32_SPI_SPI1_IRQ_PRIORITY   10

STM32_SPI_SPI1_RX_DMA_STREAM

#define STM32_SPI_SPI1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 0)

STM32_SPI_SPI1_TX_DMA_STREAM

#define STM32_SPI_SPI1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 3)

STM32_SPI_SPI2_DMA_PRIORITY

#define STM32_SPI_SPI2_DMA_PRIORITY   1

STM32_SPI_SPI2_IRQ_PRIORITY

#define STM32_SPI_SPI2_IRQ_PRIORITY   10

STM32_SPI_SPI2_RX_DMA_STREAM

#define STM32_SPI_SPI2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 3)

STM32_SPI_SPI2_TX_DMA_STREAM

#define STM32_SPI_SPI2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)

STM32_SPI_SPI3_DMA_PRIORITY

#define STM32_SPI_SPI3_DMA_PRIORITY   1

STM32_SPI_SPI3_IRQ_PRIORITY

#define STM32_SPI_SPI3_IRQ_PRIORITY   10

STM32_SPI_SPI3_RX_DMA_STREAM

#define STM32_SPI_SPI3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)

STM32_SPI_SPI3_TX_DMA_STREAM

#define STM32_SPI_SPI3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)

STM32_SPI_SPI4_DMA_PRIORITY

#define STM32_SPI_SPI4_DMA_PRIORITY   1

STM32_SPI_SPI4_IRQ_PRIORITY

#define STM32_SPI_SPI4_IRQ_PRIORITY   10

STM32_SPI_SPI4_RX_DMA_STREAM

#define STM32_SPI_SPI4_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 0)

STM32_SPI_SPI4_TX_DMA_STREAM

#define STM32_SPI_SPI4_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 1)

STM32_SPI_SPI5_DMA_PRIORITY

#define STM32_SPI_SPI5_DMA_PRIORITY   1

STM32_SPI_SPI5_IRQ_PRIORITY

#define STM32_SPI_SPI5_IRQ_PRIORITY   10

STM32_SPI_SPI5_RX_DMA_STREAM

#define STM32_SPI_SPI5_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 3)

STM32_SPI_SPI5_TX_DMA_STREAM

#define STM32_SPI_SPI5_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 4)

STM32_SPI_SPI6_DMA_PRIORITY

#define STM32_SPI_SPI6_DMA_PRIORITY   1

STM32_SPI_SPI6_IRQ_PRIORITY

#define STM32_SPI_SPI6_IRQ_PRIORITY   10

STM32_SPI_SPI6_RX_DMA_STREAM

#define STM32_SPI_SPI6_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 6)

STM32_SPI_SPI6_TX_DMA_STREAM

#define STM32_SPI_SPI6_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 5)

STM32_SPI_USE_SPI1

#define STM32_SPI_USE_SPI1   TRUE

STM32_SPI_USE_SPI2

#define STM32_SPI_USE_SPI2   FALSE

STM32_SPI_USE_SPI3

#define STM32_SPI_USE_SPI3   TRUE

STM32_SPI_USE_SPI4

#define STM32_SPI_USE_SPI4   FALSE

STM32_SPI_USE_SPI5

#define STM32_SPI_USE_SPI5   FALSE

STM32_SPI_USE_SPI6

#define STM32_SPI_USE_SPI6   FALSE

STM32_ST_IRQ_PRIORITY

#define STM32_ST_IRQ_PRIORITY   8

STM32_ST_USE_TIMER

#define STM32_ST_USE_TIMER   5

STM32_SW

#define STM32_SW   STM32_SW_PLL

STM32_UART_DMA_ERROR_HOOK

#define STM32_UART_DMA_ERROR_HOOK

(

uartp

)

osalSysHalt("DMA failure")

STM32_UART_UART4_DMA_PRIORITY

#define STM32_UART_UART4_DMA_PRIORITY   0

STM32_UART_UART4_RX_DMA_STREAM

#define STM32_UART_UART4_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 2)

STM32_UART_UART4_TX_DMA_STREAM

#define STM32_UART_UART4_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)

STM32_UART_UART5_DMA_PRIORITY

#define STM32_UART_UART5_DMA_PRIORITY   0

STM32_UART_UART5_RX_DMA_STREAM

#define STM32_UART_UART5_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)

STM32_UART_UART5_TX_DMA_STREAM

#define STM32_UART_UART5_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)

STM32_UART_USART1_DMA_PRIORITY

#define STM32_UART_USART1_DMA_PRIORITY   0

STM32_UART_USART1_RX_DMA_STREAM

#define STM32_UART_USART1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 5)

STM32_UART_USART1_TX_DMA_STREAM

#define STM32_UART_USART1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 7)

STM32_UART_USART2_DMA_PRIORITY

#define STM32_UART_USART2_DMA_PRIORITY   0

STM32_UART_USART2_RX_DMA_STREAM

#define STM32_UART_USART2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 5)

STM32_UART_USART2_TX_DMA_STREAM

#define STM32_UART_USART2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 6)

STM32_UART_USART3_DMA_PRIORITY

#define STM32_UART_USART3_DMA_PRIORITY   0

STM32_UART_USART3_RX_DMA_STREAM

#define STM32_UART_USART3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 1)

STM32_UART_USART3_TX_DMA_STREAM

#define STM32_UART_USART3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 3)

STM32_UART_USART6_DMA_PRIORITY

#define STM32_UART_USART6_DMA_PRIORITY   0

STM32_UART_USART6_RX_DMA_STREAM

#define STM32_UART_USART6_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 2)

STM32_UART_USART6_TX_DMA_STREAM

#define STM32_UART_USART6_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 7)

STM32_UART_USE_UART4

#define STM32_UART_USE_UART4   FALSE

STM32_UART_USE_UART5

#define STM32_UART_USE_UART5   FALSE

STM32_UART_USE_USART1

#define STM32_UART_USE_USART1   FALSE

STM32_UART_USE_USART2

#define STM32_UART_USE_USART2   FALSE

STM32_UART_USE_USART3

#define STM32_UART_USE_USART3   FALSE

STM32_UART_USE_USART6

#define STM32_UART_USE_USART6   FALSE

STM32_USB_HOST_WAKEUP_DURATION

#define STM32_USB_HOST_WAKEUP_DURATION   2

STM32_USB_OTG1_IRQ_PRIORITY

#define STM32_USB_OTG1_IRQ_PRIORITY   11

STM32_USB_OTG1_RX_FIFO_SIZE

#define STM32_USB_OTG1_RX_FIFO_SIZE   512

STM32_USB_OTG2_IRQ_PRIORITY

#define STM32_USB_OTG2_IRQ_PRIORITY   14

STM32_USB_OTG2_RX_FIFO_SIZE

#define STM32_USB_OTG2_RX_FIFO_SIZE   1024

STM32_USB_USE_OTG1

#define STM32_USB_USE_OTG1   TRUE

STM32_USB_USE_OTG2

#define STM32_USB_USE_OTG2   FALSE

STM32_WDG_USE_IWDG

#define STM32_WDG_USE_IWDG   FALSE

STM32F427_MCUCONF

#define STM32F427_MCUCONF

STM32F429_MCUCONF

#define STM32F429_MCUCONF

STM32F437_MCUCONF

#define STM32F437_MCUCONF

STM32F439_MCUCONF

#define STM32F439_MCUCONF

STM32F4xx_MCUCONF

#define STM32F4xx_MCUCONF